1. Field of the Invention
This invention relates to semiconductor wafer manufacturing and, more specifically, to a method for doping in two separate steps a gate conductor of an NMOS or PMOS device for optimal conductivity along with minimal opportunity for migration of the dopants from the gate conductor and through the underlying gate dielectric.
2. Description of Relevant Art
Fabrication of a metal-oxide-semiconductor ("MOS") transistor is well-known. The manufacturing process begins by lightly doping a single-crystal silicon substrate n-type or p-type. The active areas where the transistors and other devices will be formed are then isolated from other active areas with isolation structures. Isolation structures may comprise shallow trenches in the substrate filled with a dielectric. Isolation structures may alternatively comprise local oxidation of silicon ("LOCOS") structures. A gate dielectric is then formed by thermally oxidizing the silicon substrate. This oxidation may be performed in a thermal oxidation furnace or, alternatively, in a rapid-thermal-anneal apparatus. A gate conductor may be formed by depositing polycrystalline silicon ("polysilicon") upon a dielectric-covered semiconductor substrate and then patterning the polysilicon using typical masking and etching techniques. Subsequently, the polysilicon and source/drain regions are concurrently doped, using ion implantation, usually with a high dosage n-type or p-type dopant. If the impurity dopant is n-type, then the resulting transistor is referred to as a NMOS device. Conversely, if the impurity dopant is p-type, then the resulting transistor is referred to as a PMOS device.
The resistivity of the polysilicon gate structure is reduced by the introduction of impurities into the structure. Enough dopants are introduced so that the sheet resistivity of the gate conductive structures can be reduced to, in some instances, less than approximately 500 ohms/sq. The polysilicon is implanted during the same process step that the source and drain regions are implanted. In an ion implantation process, the depth at which the dopants are implanted can be controlled by adjusting the energy given to the ions by the ion implantation equipment. Ions with higher energy are introduced deeper into the polysilicon. In most cases, implantation into the crystalline source/drain areas through an implant displacement layer which serves to minimize implant channeling and unwanted contaminants from being forwarded into the crystalline material. During subsequent heat processing often needed for example during implant anneal, the implanted dopants further diffuse to assume their final position in the polysilicon gate structure. Dopants with a high diffusivity typically migrate to greater depths within the polysilicon gate than dopants with low diffusivity. Additionally, the bottom interface of the polysilicon layer must be doped to a sufficiently high level to properly control the turn-on characteristics of the transistor.
For modern MOS type transistors, the source and drain regions need to be very shallow. Shallow source and drain regions help reduce susceptibility to short-channel effects, make the device less prone to punchthrough effects, and reduce parasitic capacitance. By reducing the vertical depth of the source and drain regions, the lateral spread of the dopants in these regions beneath the gate structure also becomes smaller. Hence, a longer effective channel is possible for a fixed gate length. To achieve shallow source and drain regions, relatively low implantation energies are used to ensure that the dopants are implanted close to the upper surface of the semiconductor substrate. Since source/drain and gate conductor doping is concurrent, shallow dopants within the source/drain area are also placed a shallow depth within the gate conductor, just below the gate conductor upper surface.
For an NMOS device, arsenic is typically used to dope the polysilicon gate and the source/drain region. Arsenic is a slow diffuser and will not readily migrate even during substantial heat treatment. As a result, the upper portion of the gate conductor receives arsenic and the lower portion generally remains undoped. The undoped lower portion acts as a high resistivity region which deleterious hinders performance of the gate conductor. The high resistivity lower portion not only increases overall resistivity of the gate conductor but also increases the "turn-on" characteristics of the ensuring transistor--possibly beyond an acceptable design limit.
For a PMOS device, boron may be used to dope the gate conductor as well as the source/drain region of the transistor. Boron is typically implanted a fixed distance from the upper surface of the polysilicon which is approximately the same as the distance in which the source/drain implant is implanted from the upper surface of the gate oxide. Boron is considered a fast diffuser and will migrate significantly with subsequent heat processing. As a result, the boron may diffuse from the gate conductor through the gate oxide and into the channel region of the transistor. The presence of boron in the channel may change the doping concentration in the channel which will result in a threshold voltage shift possibly beyond acceptable levels. Boron penetration into the channel can also cause other undesirable effects such as an increase in electron trapping, a decrease in low-field hole mobility, and degradation of current drive.
It would be desirable to derive a fabrication process which can optimally place high diffusivity and/or low diffusivity dopants in the gate conductor so as to ensure a fairly uniform dopant profile throughout a gate conductor cross-section after subsequent heat treatments. The desired fabrication process must be one which can optimally place both high and low diffusivity dopants with a view towards minimizing segregation and migration of highly mobile dopants into the underlying gate dielectric.